J.-P. Han
J.-P. Han
IBM T. J. Watson Research Center
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Why is nonvolatile ferroelectric memory field-effect transistor still elusive?
TP Ma, JP Han
IEEE Electron Device Letters 23 (7), 386-388, 2002
Mobility measurement and degradation mechanisms of MOSFETs made with ultrathin high-k dielectrics
W Zhu, JP Han, TP Ma
IEEE Transactions on Electron Devices 51 (1), 98-105, 2004
Ferroelectric field effect transistors for memory applications
J Hoffman, X Pan, JW Reiner, FJ Walker, JP Han, CH Ahn, TP Ma
Advanced materials 22 (26‐27), 2957-2961, 2010
Electrode dependence of hydrogen-induced degradation in ferroelectric and thin films
JP Han, TP Ma
Applied physics letters 71 (9), 1267-1269, 1997
NVM neuromorphic core with 64k-cell (256-by-256) phase change memory synaptic array with on-chip neuron circuits for continuous in-situ learning
S Kim, M Ishii, S Lewis, T Perri, M BrightSky, W Kim, R Jordan, GW Burr, ...
2015 IEEE international electron devices meeting (IEDM), 17.1. 1-17.1. 4, 2015
memory capacitor on Si with a silicon nitride buffer
JP Han, TP Ma
Applied physics letters 72 (10), 1185-1186, 1998
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
S Krishnan, U Kwon, N Moumen, MW Stoker, ECT Harley, S Bedell, ...
2011 International Electron Devices Meeting, 28.1. 1-28.1. 4, 2011
A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process
X Chen, S Samavedam, V Narayanan, K Stein, C Hobbs, C Baiocco, W Li, ...
2008 Symposium on VLSI Technology, 88-89, 2008
Ferroelectric dynamic random access memory
TP Ma, JP Han
US Patent 6,067,244, 2000
High inversion current in silicon nanowire field effect transistors
SM Koo, A Fujiwara, JP Han, EM Vogel, CA Richter, JE Bonevich
Nano Letters 4 (11), 2197-2201, 2004
Si-doped aluminates for high temperature metal-gate CMOS: Zr-Al-Si-O, a novel gate dielectric for low power applications
L Manchanda, ML Green, RB Van Dover, MD Morris, A Kerber, Y Hu, ...
International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No …, 2000
Ferroelectric DRAM (FEDRAM) FET with metal/SrBi2Ta2O/sub 9//SiN/Si gate structure
KH Kim, JP Han, SW Jung, TP Ma
IEEE Electron Device Letters 23 (2), 82-84, 2002
Fabrication of 50–100 nm patterned InGaN blue light emitting heterostructures
L Chen, A Yin, JS Im, AV Nurmikko, JM Xu, J Han
physica status solidi (a) 188 (1), 135-138, 2001
Competitive and cost effective high-k based 28nm CMOS technology for low power applications
F Arnaud, A Thean, M Eller, M Lipinski, YW Teh, M Ostermayr, K Kang, ...
2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009
Transistor mismatch properties in deep-submicrometer CMOS technologies
X Yuan, T Shimizu, U Mahalingam, JS Brown, KZ Habib, DG Tekleab, ...
IEEE Transactions on Electron Devices 58 (2), 335-342, 2011
Electron Device Lett
KH Kim, JP Han, SW Jung, TP Ma
IEEE 23, 82, 2002
Asymmetric energy distribution of interface traps in n-and p-MOSFETs with HfO/sub 2/gate dielectricon ultrathin SiON buffer layer
JP Han, EM Vogel, EP Gusev, C D'Emic, CA Richter, DW Heh, JS Suehle
IEEE Electron Device Letters 25 (3), 126-128, 2004
Confined PCM-based analog synaptic devices offering low resistance-drift and 1000 programmable states for deep learning
W Kim, RL Bruce, T Masuda, GW Fraczak, N Gong, P Adusumilli, ...
2019 Symposium on VLSI Technology, T66-T67, 2019
Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same
JP Han, A Gutmann, R Knoefler, J Yan, C Stapelmann, J Lian, YF Chong
US Patent 7,800,182, 2010
Methods of fabricating semiconductor devices and structures thereof
K Stahrenberg, JP Han
US Patent 8,252,649, 2012
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