Teyuh Chou
Cited by
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3D Ta/TaO x/TiO2/Ti synaptic array and linearity tuning of weight update for hardware neural network applications
IT Wang, CC Chang, LW Chiu, T Chou, TH Hou
Nanotechnology 27 (36), 365204, 2016
Mitigating asymmetric nonlinear weight update effects in hardware neural network based on analog resistive synapse
CC Chang, PC Chen, T Chou, IT Wang, B Hudec, CC Chang, CM Tsai, ...
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8 (1á…, 2017
CASCADE: Connecting RRAMs to Extend Analog Dataflow In An End-To-End In-Memory Processing Paradigm
T Chou, W Tang, J Botimer, Z Zhang
Proceedings of the 52nd Annual IEEE/ACM International Symposium oná…, 2019
Challenges and opportunities toward online training acceleration using RRAM-based hardware neural network
CC Chang, JC Liu, YL Shen, T Chou, PC Chen, IT Wang, CC Su, MH Wu, ...
2017 IEEE International Electron Devices Meeting (IEDM), 11.6. 1-11.6. 4, 2017
A 1.87-mm▓ 56.9-GOPS Accelerator for Solving Partial Differential Equations
T Chen, J Botimer, T Chou, Z Zhang
IEEE Journal of Solid-State Circuits, 2020
An Sram-Based Accelerator for Solving Partial Differential Equations
T Chen, J Botimer, T Chou, Z Zhang
2019 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2019
Neuromorphic pattern learning using HBM electronic synapse with excitatory and inhibitory plasticity
T Chou, JC Liu, LW Chiu, IT Wang, CM Tsai, TH Hou
2015 International Symposium on VLSI Technology, Systems and Applications, 1-2, 2015
NetFlex: A 22nm Multi-Chiplet Perception Accelerator in High-Density Fan-Out Wafer-Level Packaging
T Chou, W Tang, MD Rotaru, C Liu, R Dutta, SLP Siang, DHS Wee, ...
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology andá…, 2022
Development of three-dimensional synaptic device and neuromorphic computing hardware
IT Wang, T Chou, LW Chiu, CC Chang, TH Hou
2016 13th IEEE International Conference on Solid-State and Integratedá…, 2016
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