| Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench: The System Architect's Workbench DE Thomas, ED Lagnese, RA Walker, JV Rajan, RL Blackburn, JA Nestor Springer Science & Business Media, 1989 | 254 | 1989 |
| Behavioral synthesis with interface JA Nestor IEEE/ACM Int. Conf. CAD, 112-115, 1986 | 133 | 1986 |
| SALSA: A new approach to scheduling with timing constraints JA Nestor, G Krishnamoorthy IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1993 | 110 | 1993 |
| A new look at hardware maze routing JA Nestor Proceedings of the 12th ACM Great Lakes symposium on VLSI, 142-147, 2002 | 97 | 2002 |
| Data path allocation using an extended binding model G Krishnamoorthy, JA Nestor Annual ACM IEEE Design Automation Conference: Proceedings of the 29 th ACM …, 1992 | 70 | 1992 |
| Specification and synthesis of digital systems with interfaces JA Nestor Carnegie Mellon University, 1987 | 42 | 1987 |
| Defining and implementing a multilevel design representation with simulation applications JA Nestor, DE Thomas 19th Design Automation Conference, 740-746, 1982 | 20 | 1982 |
| Defining and implementing a multilevel design representation with simulation applications JA Nestor, DE Thomas 19th Design Automation Conference, 740-746, 1982 | 20 | 1982 |
| Teaching computer organization with HDLs: An incremental approach JA Nestor 2005 IEEE International Conference on Microelectronic Systems Education (MSE …, 2005 | 17 | 2005 |
| SALSA II: A fast transformational scheduler for high-level synthesis MR Rhinehart, J Nestor 1993 IEEE International Symposium on Circuits and Systems (ISCAS), 1678-1681, 1993 | 16 | 1993 |
| MIES: a microarchitecture design tool JA Nestor, B Soudan, Z Mayet Proceedings of the 22nd annual workshop on Microprogramming and …, 1989 | 15 | 1989 |
| Experience with the CADAPPLETS Project JA Nestor IEEE Transactions on Education 51 (3), 342-348, 2008 | 9 | 2008 |
| L3: An FPGA-based multilayer maze routing accelerator JA Nestor Microprocessors and Microsystems 29 (2-3), 87-97, 2005 | 7 | 2005 |
| Integrating digital, analog, and mixed-signal design in an undergraduate ECE curriculum JA Nestor, DA Rich Proceedings 2003 IEEE International Conference on Microelectronic Systems …, 2003 | 7 | 2003 |
| Visual register-transfer description of VLSI microarchitectures JA Nestor IEEE Transactions on Very Large Scale Integration (VLSI) Systems 1 (1), 72-76, 1993 | 7 | 1993 |
| FPGA implementation of a maze routing accelerator JA Nestor Field Programmable Logic and Application: 13th International Conference, FPL …, 2003 | 6 | 2003 |
| Exploiting scheduling freedom in controller synthesis JA Nestor, V Tamas Proceedings of the Sixth International Workshop on High-Level Synthesis, 74-86, 1992 | 6 | 1992 |
| Work in progress-a new course on Intellectual Property, innovation, and ethics JA Nestor 2009 39th IEEE Frontiers in Education Conference, 1-2, 2009 | 5 | 2009 |
| L4: An FPGA-based accelerator for detailed maze routing JA Nestor, J Lavine 2007 International Conference on Field Programmable Logic and Applications …, 2007 | 5 | 2007 |
| An undergraduate embedded systems project JF Greco, JA Nestor 2011 IEEE International Conference on Microelectronic Systems Education, 43-46, 2011 | 4 | 2011 |
Bassel SoudanUniversity of SharjahVerified email at sharjah.ac.ae
