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Qun Gao
Qun Gao
Department of Electrical and Computer Engineering, University of Florida
Verified email at ufl.edu
Title
Cited by
Cited by
Year
One-dimensional electrical contact to a two-dimensional material
L Wang, I Meric, PY Huang, Q Gao, Y Gao, H Tran, T Taniguchi, ...
Science 342 (6158), 614-617, 2013
31112013
Ballistic InAs nanowire transistors
S Chuang, Q Gao, R Kapadia, AC Ford, J Guo, A Javey
Nano letters 13 (2), 555-558, 2013
2122013
Quantum confinement effects in nanoscale-thickness InAs membranes
K Takei, H Fang, SB Kumar, R Kapadia, Q Gao, M Madsen, HS Kim, ...
Nano letters 11 (11), 5008-5012, 2011
1202011
Stabilized compositions and processes of their preparation
R Nunes, M Heisey, G Downton, L Evers-Smith
US Patent App. 10/014,364, 2003
302003
Role of chemical termination in edge contact to graphene
Q Gao, J Guo
APL Materials 2 (5), 2014
262014
Asymmetric formation of epi semiconductor material in source/drain regions of FinFET devices
A Arya, B Greene, Q Gao, C Nassar, J Hong, V Chhabra
US Patent 10,269,932, 2019
192019
Barrier height determination of silicide-silicon contact by hybrid density functional simulation
Q Gao, J Guo
Applied Physics Letters 99 (18), 2011
142011
Ab initio quantum transport simulation of silicide-silicon contacts
Q Gao, J Guo
Journal of Applied Physics 111 (1), 2012
132012
Two-dimensional quantum mechanical modeling of silicide–silicon contact resistance for nanoscale silicon-on-insulator metal-oxide-semiconductor field effect transistor
Q Gao, Y Ouyang, J Guo
Journal of Applied Physics 109 (10), 2011
82011
Dynamic On-resistance and Tunneling Based De-trapping in GaN HEMT
L Zhu, KH Teo, Q Gao
2015 IEEE Conference on Electron Devices and Solid-State Circuits, 2015
52015
Finfet device comprising a piezoelectric liner for generating a surface charge and methods of making such a device
Q Gao, N Siddiqui, AI Chou
US Patent App. 15/657,373, 2019
42019
H. a. Bechtel, J. Guo, A. Javey
K Takei, H Fang, SB Kumar, R Kapadia, Q Gao, M Madsen, HS Kim, ...
Nano Lett 11, 5008, 2011
42011
Method for analyzing discrete traps in semiconductor devices
A Kniazev, Q Gao, KH Teo
US Patent 9,691,861, 2017
32017
An extrinsic device and leakage mechanism in advanced bulk FinFET SRAM
RW Mann, M Zhao, S Parihar, Q Gao, A Arya, C Radens, SM Pandey, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (8 …, 2019
22019
Innovative use of FA techniques SCM and OBIRCH along with TCAD to resolve junction scaling issues at advanced technology nodes
G Johnson, J Nxumalo, A Arya, J Johnson, Q Gao, B Greene
2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC …, 2018
22018
Fin reveal forming STI regions having convex shape between fins
XU Yiheng, H Wang, Q Gao, S Beasor, KB Koo, A Arya
US Patent 10,832,965, 2020
12020
Fin-type transistors with spacers on the gates
S Yanping, H Zang, HC Lo, Q Gao, J Ciavatti, Y Qi, W Hong, Y Shi, JG Lee, ...
US Patent 10,636,894, 2020
12020
Composite sacrificial gate with etch selective layer
Q Gao, N Siddiqui, A Arya, JR Sporre
US Patent 10,593,555, 2020
12020
Gate skirt oxidation for improved finfet performance and method for producing the same
Q Gao, C Nassar, S Krishnamurthy, DAF LUPPI, J Sporre, S Siddiqui, ...
US Patent App. 15/943,272, 2019
12019
First Principles Calculations of the Effect of Stress in the I-V Characteristics of the CoSi2/Si Interface
OD Restrepo, Q Gao, SM Pandey, E Cruz-Silva, EM Bazizi
2018 International Conference on Simulation of Semiconductor Processes and …, 2018
12018
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Articles 1–20