| Energy-efficient convolution architecture based on rescheduled dataflow J Jo, S Kim, IC Park IEEE Transactions on Circuits and Systems I: Regular Papers 65 (12), 4196-4207, 2018 | 61 | 2018 |
| Real-time SSDLite object detection on FPGA S Kim, S Na, BY Kong, J Choi, IC Park IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (6 …, 2021 | 25 | 2021 |
| High-speed counter with novel LFSR state extension H Bae, Y Hyun, S Kim, S Park, J Lee, B Jang, S Choi, IC Park IEEE Transactions on Computers 72 (3), 893-899, 2022 | 6 | 2022 |
| A CNN inference accelerator on FPGA with compression and layer-chaining techniques for style transfer applications S Kim, B Jang, J Lee, H Bae, H Jang, IC Park IEEE Transactions on Circuits and Systems I: Regular Papers 70 (4), 1591-1604, 2023 | 5 | 2023 |
| Hybrid convolution architecture for energy-efficient deep neural network processing S Kim, J Jo, IC Park IEEE Transactions on Circuits and Systems I: Regular Papers 68 (5), 2017-2029, 2021 | 4 | 2021 |
