Shreesha Srinath
Shreesha Srinath
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Design and implementation of an" approximate" communication system for wireless media applications
S Sen, S Gilani, S Srinath, S Schmitt, S Banerjee
Proceedings of the ACM SIGCOMM 2010 Conference, 15-26, 2010
A modular digital VLSI flow for high-productivity SoC design
B Khailany, E Krimer, R Venkatesan, J Clemons, JS Emer, M Fojtik, ...
2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), 1-6, 2018
Microarchitectural mechanisms to exploit value structure in SIMT architectures
J Kim, C Torng, S Srinath, D Lockhart, C Batten
Proceedings of the 40th Annual International Symposium on Computer …, 2013
Architectural specialization for inter-iteration loop dependence patterns
S Srinath, B Ilbeyi, M Tan, G Liu, Z Zhang, C Batten
2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 583-595, 2014
Dynamic hazard resolution for pipelining irregular loops in high-level synthesis
S Dai, R Zhao, G Liu, S Srinath, U Gupta, C Batten, Z Zhang
Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017
Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks
S Srinath, K Compton
Proceedings of the 18th annual ACM/SIGDA international symposium on Field …, 2010
An architectural framework for accelerating dynamic parallel algorithms on reconfigurable hardware
T Chen, S Srinath, C Batten, GE Suh
2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018
Improving high-level synthesis with decoupled data structure optimization
R Zhao, G Liu, S Srinath, C Batten, Z Zhang
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2016
Using intra-core loop-task accelerators to improve the productivity and performance of task-based parallel programs
J Kim, S Jiang, C Torng, M Wang, S Srinath, B Ilbeyi, K Al-Hawa, C Batten
2017 50th Annual IEEE/ACM International Symposium on Microarchitecture …, 2017
Accelerating a PARSEC benchmark using portable subword SIMD
S Ghose, S Srinath, J Tse
CS 5220: Final Project Report. Sch. of Elec. and Comp. Eng., Cornell Eng, 2011
Rough neuron based neural classifier
A Kothari, A Keskar, R Chalasani, S Srinath
2008 First International Conference on Emerging Trends in Engineering and …, 2008
Experiences using a novel Python-based hardware modeling framework for computer architecture test chips.
C Torng, M Wang, B Sudheendra, N Murali, S Jayasuriya, S Srinath, ...
Hot Chips Symposium, 1, 2016
Lane-Based Hardware Specialization for Loop-and Fork-Join-Centric Parallelization and Scheduling Strategies
S Srinath
Cornell University, 2018
Design and Implementation of an “Approximate” Communication System for Wireless Media Applications
S Sen, T Zhang, S Gilani, S Srinath, S Banerjee, S Addepalli
IEEE/ACM Transactions on Networking 21 (4), 1035-1048, 2012
Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation
N Kabylkas, T Thorn, S Srinath, P Xekalakis, J Renau
MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture …, 2021
Exploring realizations of large integer multipliers using embedded blocks in modern FPGAs.
S Srinath
Feature Space Reductions Using Rough Sets for a Rough-Neuro Hybrid Approach Based Pattern Classifier
A Kothari, A Gokhale, A Keskar, S Srinath, R Chalasani
CS 5220: Project 3 All-Pairs Shortest Path
S Ghose, S Srinath, J Tse
CS 5220: Project 2 Smoothed Particle Hydrodynamics
S Ghose, S Srinath, J Tse
XLOOPS: Explicit Loop Specialization
S Srinath, B Ilbeyi, M Tan, G Liu, Z Zhang, C Batten
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