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Priyanka Raina
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Timeloop: A Systematic Approach to DNN Accelerator Evaluation
A Parashar, P Raina, YS Shao, YH Chen, VA Ying, A Mukkara, ...
2019 IEEE International Symposium on Performance Analysis of Systems and …, 2019
206*2019
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture
YS Shao, J Clemons, R Venkatesan, B Zimmer, M Fojtik, N Jiang, B Keller, ...
Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019
1572019
Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators
X Yang, M Gao, Q Liu, J Setter, J Pu, A Nayak, S Bell, K Cao, H Ha, ...
Proceedings of the Twenty-Fifth International Conference on Architectural …, 2020
1042020
MAGNet: A Modular Accelerator Generator for Neural Networks
R Venkatesan, YS Shao, M Wang, J Clemons, S Dai, M Fojtik, B Keller, ...
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019
632019
A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models
W Wan, R Kubendran, SB Eryilmaz, W Zhang, Y Liao, D Wu, S Deiss, ...
2020 IEEE International Solid-State Circuits Conference (ISSCC), 498-500, 2020
592020
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm
B Zimmer, R Venkatesan, YS Shao, J Clemons, M Fojtik, N Jiang, B Keller, ...
2019 Symposium on VLSI Circuits, C300-C301, 2019
44*2019
A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm
B Zimmer, R Venkatesan, YS Shao, J Clemons, M Fojtik, N Jiang, B Keller, ...
IEEE Journal of Solid-State Circuits (JSSC) 55 (4), 920-932, 2020
382020
A Voltage-Mode Sensing Scheme with Differential-Row Weight Mapping for Energy-Efficient RRAM-Based In-Memory Computing
W Wan, R Kubendran, B Gao, S Josbi, P Raina, H Wu, G Cauwenberghs, ...
2020 IEEE Symposium on VLSI Technology, 1-2, 2020
152020
Chimera: A 0.92 tops, 2.2 tops/w edge ai accelerator with 2 mbyte on-chip foundry resistive ram for efficient training and inference
M Giordano, K Prabhu, K Koul, RM Radway, A Gural, R Doshi, ZF Khan, ...
2021 Symposium on VLSI Circuits, 1-2, 2021
132021
Reconfigurable Processor for Energy-Efficient Computational Photography
R Rithe, P Raina, N Ickes, SV Tenneti, AP Chandrakasan
IEEE Journal of Solid-State Circuits (JSSC) 48 (11), 2908-2919, 2013
112013
A 0.6V 8mW 3D Vision Processor for a Navigation Device for the Visually Impaired
D Jeon, N Ickes, P Raina, HC Wang, D Rus, A Chandrakasan
2016 IEEE International Solid-State Circuits Conference (ISSCC), 416-417, 2016
102016
Vascular events In noncardiac Surgery patIents cOhort evaluatioN VISION Study Investigators. Myocardial injury after noncardiac surgery: a large, international, prospective …
F Botto, P Alonso-Coello, MT Chan, JC Villar, D Xavier, S Srinathan, ...
Anesthesiology 120 (3), 564-578, 2014
102014
Sapiens: A 64-kb rram-based non-volatile associative memory for one-shot learning and inference at the edge
H Li, WC Chen, A Levy, CH Wang, H Wang, PH Chen, W Wan, WS Khwa, ...
IEEE Transactions on Electron Devices 68 (12), 6637-6643, 2021
92021
Creating an Agile Hardware Design Flow
R Bahr, C Barrett, N Bhagdikar, A Carsello, R Daly, C Donovick, D Durst, ...
2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020
92020
Reconfigurable Processor for Energy-Scalable Computational Photography
R Rithe, P Raina, N Ickes, SV Tenneti, AP Chandrakasan
2013 IEEE International Solid-State Circuits Conference (ISSCC), 164-165, 2013
92013
A 0.11 pj/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology
R Venkatesan, YS Shao, B Zimmer, J Clemons, M Fojtik, N Jiang, B Keller, ...
2019 IEEE Hot Chips 31 Symposium (HCS), 1-24, 2019
72019
Automating Vitiligo skin lesion segmentation using convolutional neural networks
M Low, V Huang, P Raina
2020 IEEE 17th International Symposium on Biomedical Imaging (ISBI), 1-4, 2020
62020
One-shot learning with memory-augmented neural networks using a 64-kbit, 118 GOPS/W RRAM-based non-volatile associative memory
H Li, WC Chen, A Levy, CH Wang, H Wang, PH Chen, W Wan, HSP Wong, ...
2021 Symposium on VLSI Technology, 1-2, 2021
52021
Simba: Scaling Deep-Learning Inference with Chiplet-Based Architecture
YS Shao, J Cemons, R Venkatesan, B Zimmer, M Fojtik, N Jiang, B Keller, ...
Communications of the ACM 64 (6), 107-116, 2021
52021
An Energy-Scalable Accelerator for Blind Image Deblurring
P Raina, M Tikekar, AP Chandrakasan
IEEE Journal of Solid-State Circuits (JSSC) 52 (7), 1849-1862, 2017
52017
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Articles 1–20