| A survey on machine learning accelerators and evolutionary hardware platforms S Bavikadi, A Dhavlle, A Ganguly, A Haridass, H Hendy, C Merkel, ... IEEE Design & Test 39 (3), 91-116, 2022 | 33 | 2022 |
| Application and thermal-reliability-aware reinforcement learning based multi-core power management SMP Dinakarrao, A Joseph, A Haridass, M Shafique, J Henkel, ... ACM Journal on Emerging Technologies in Computing Systems (JETC) 15 (4), 1-19, 2019 | 28 | 2019 |
| System level power profiling of embedded applications executing on virtual multicore system-on-chip platforms NR Dhanwada, J Arun, WW Dungan US Patent 8,898,049, 2014 | 24 | 2014 |
| Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis N Dhanwada, D Hathaway, V Zyuban, P Peng, K Moody, W Dungan, ... 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 458-465, 2013 | 22 | 2013 |
| Method for Process Synchronization of Embedded Applications in Multi-Core Systems NNR Dhanwada, A Joseph US Patent App. 12/913,880, 2012 | 17 | 2012 |
| System to monitor computing hardware in a computing infrastructure facility VS Venkatesan, A Haridass, DBC Vidyapoornachary, A Joseph US Patent 11,221,905, 2022 | 7 | 2022 |
| Optimization through use of conductive threads and biometric data AK Baughman, A Joseph, BM O'connell, D Pandey US Patent 10,180,688, 2019 | 5 | 2019 |
| Formal verification driven power modeling and design verification A Haridass, A Joseph, PK Nalla, RM Rao US Patent 9,697,306, 2017 | 5 | 2017 |
| Empirically derived abstractions in uncore power modeling for a server-class processor chip H Jacobson, A Joseph, D Parikh, P Bose, A Buyuktosunoglu Proceedings of the 2014 international symposium on Low power electronics and …, 2014 | 5 | 2014 |
| Leakage power characterization at high temperatures for an integrated circuit DBC Vidyapoornachary, A Haridass, A Joseph, CR Lefurgy, ... US Patent 10,031,180, 2018 | 4 | 2018 |
| Memory power management and data consolidation DBC Vidyapoornachary, ER Cordero, A Haridass, A Joseph US Patent 9,606,741, 2017 | 4 | 2017 |
| Memory power management and data consolidation DBC Vidyapoornachary, ER Cordero, A Haridass, A Joseph US Patent 9,606,741, 2017 | 4 | 2017 |
| Formal verification driven power modeling and design verification A Haridass, A Joseph, PK Nalla, RM Rao US Patent 9,460,251, 2016 | 4 | 2016 |
| Hierarchical power analysis using improved activity abstraction and capacitance abstraction by accounting for design heterogeneity extremities A Joseph, SV Rachamalla, R Rao, S Reddy US Patent 11,036,905, 2021 | 3 | 2021 |
| Methods for generating a contributor-based power abstract for a device NR Dhanwada, WW Dungan, DJ Hathaway, A Joseph, G Mittal, ... US Patent 10,460,048, 2019 | 3 | 2019 |
| On the fly netlist compression in power analysis A Joseph, RM Rao US Patent 9,996,649, 2018 | 3 | 2018 |
| Early analysis and mitigation of self-heating in design flows NR Dhanwada, WW Dungan, A Joseph, S Lee, AA Mets, ... US Patent 9,990,454, 2018 | 3 | 2018 |
| Cross-current power modelling using logic simulation A Joseph, A Madhusoodanan, RM Rao, ST Skariah US Patent 9,916,406, 2018 | 3 | 2018 |
| Method for breaking down hardware power into sub-components NR Dhanwada, A Haridass, A Joseph, CR Lefurgy, D Pandey US Patent 9,217,771, 2015 | 3 | 2015 |
| Virtual logic netlist: Enabling efficient RTL analysis S Rachamalla, A Joseph, R Rao, D Pandey Sixteenth International Symposium on Quality Electronic Design, 571-576, 2015 | 3 | 2015 |
Anand HaridassMicrosoft Corporation - Azure HW Systems & Infra (AHSI)Verified email at microsoft.com
