Antonio Pullini
Antonio Pullini
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Design issues and considerations for low-cost 3-D TSV IC technology
G Van der Plas, P Limaye, I Loi, A Mercha, H Oprins, C Torregiani, S Thijs, ...
IEEE Journal of Solid-State Circuits 46 (1), 293-307, 2010
Near-threshold RISC-V core with DSP extensions for scalable IoT endpoint devices
M Gautschi, PD Schiavone, A Traber, I Loi, A Pullini, D Rossi, E Flamand, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (10 …, 2017
Network-on-chip design and synthesis outlook
D Atienza, F Angiolini, S Murali, A Pullini, L Benini, G De Micheli
Integration 41 (3), 340-359, 2008
GAP-8: A RISC-V SoC for AI at the Edge of the IoT
E Flamand, D Rossi, F Conti, I Loi, A Pullini, F Rotenberg, L Benini
2018 IEEE 29th International Conference on Application-specific Systems …, 2018
Fault tolerance overhead in network-on-chip flow control schemes
A Pullini, F Angiolini, D Bertozzi, L Benini
2005 18th Symposium on Integrated Circuits and Systems Design, 224-229, 2005
An IoT endpoint system-on-chip for secure and energy-efficient near-sensor analytics
F Conti, R Schilling, PD Schiavone, A Pullini, D Rossi, FK Gürkaynak, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 64 (9), 2481-2494, 2017
Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications
PD Schiavone, F Conti, D Rossi, M Gautschi, A Pullini, E Flamand, ...
2017 27th International Symposium on Power and Timing Modeling, Optimization …, 2017
PULP: A parallel ultra low power platform for next generation IoT applications
D Rossi, F Conti, A Marongiu, A Pullini, I Loi, M Gautschi, G Tagliavini, ...
2015 IEEE Hot Chips 27 Symposium (HCS), 1-39, 2015
Bringing NoCs to 65 nm
A Pullini, F Angiolini, S Murali, D Atienza, G De Micheli, L Benini
IEEE Micro 27 (5), 75-85, 2007
PULP: A ultra-low power parallel accelerator for energy-efficient and flexible embedded vision
F Conti, D Rossi, A Pullini, I Loi, L Benini
Journal of Signal Processing Systems 84 (3), 339-354, 2016
Mr. Wolf: An energy-precision scalable parallel ultra low power SoC for IoT edge processing
A Pullini, D Rossi, I Loi, G Tagliavini, L Benini
IEEE Journal of Solid-State Circuits 54 (7), 1970-1981, 2019
NoC design and implementation in 65nm technology
A Pullini, F Angiolini, P Meloni, D Atienza, S Murali, L Raffo, G De Micheli, ...
First International Symposium on Networks-on-Chip (NOCS'07), 273-282, 2007
Networks on chips: From research to products
G De Micheli, C Seiculescu, S Murali, L Benini, F Angiolini, A Pullini
Proceedings of the 47th Design Automation Conference, 300-305, 2010
A 60 gops/w,− 1.8 v to 0.9 v body bias ulp cluster in 28 nm utbb fd-soi technology
D Rossi, A Pullini, I Loi, M Gautschi, FK Gürkaynak, A Bartolini, ...
Solid-State Electronics 117, 170-184, 2016
Energy-efficient near-threshold parallel computing: The PULPv2 cluster
D Rossi, A Pullini, I Loi, M Gautschi, FK Gürkaynak, A Teman, ...
Ieee Micro 37 (5), 20-31, 2017
PULPino: A small single-core RISC-V SoC
A Traber, F Zaruba, S Stucki, A Pullini, G Haugou, E Flamand, ...
3rd RISCV Workshop, 2016
193 MOPS/mW@ 162 MOPS, 0.32 V to 1.15 V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing
D Rossi, A Pullini, I Loi, M Gautschi, FK Gurkaynak, A Teman, ...
2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX), 1-3, 2016
Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis
S Bobba, J Zhang, A Pullini, D Atienza, G De Micheli
2009 Design, Automation & Test in Europe Conference & Exhibition, 616-621, 2009
Timing-driven row-based power gating
A Sathanur, A Pullini, L Benini, A Macii, E Macii, M Poncino
Proceedings of the 2007 international symposium on Low power electronics and …, 2007
Mr. wolf: A 1 gflop/s energy-proportional parallel ultra low power soc for iot edge processing
A Pullini, D Rossi, I Loi, A Di Mauro, L Benini
ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference (ESSCIRC …, 2018
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