Michael H Perrott
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A 12-Bit, 10-MHz Bandwidth, Continuous-Time ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer
MZ Straayer, MH Perrott
IEEE journal of solid-state circuits 43 (4), 805-814, 2008
A multi-path gated ring oscillator TDC with first-order noise shaping
MZ Straayer, MH Perrott
IEEE Journal of Solid-State Circuits 44 (4), 1089-1098, 2009
Photonic ADC: overcoming the bottleneck of electronic jitter
A Khilo, SJ Spector, ME Grein, AH Nejadmalayeri, CW Holzwarth, ...
Optics Express 20 (4), 4454-4469, 2012
A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation
MH Perrott, TL Tewksbury, CG Sodini
IEEE journal of solid-state circuits 32 (12), 2048-2060, 1997
A Low-Noise Wide-BW 3.6-GHz Digital Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation
CM Hsu, MZ Straayer, MH Perrott
IEEE Journal of Solid-State Circuits 43 (12), 2776-2786, 2008
A modeling approach for/spl Sigma/-/spl Delta/fractional-N frequency synthesizers allowing straightforward noise analysis
MH Perrott, MD Trott, CG Sodini
IEEE Journal of Solid-State Circuits 37 (8), 1028-1038, 2002
Digital compensation for wideband modulation of a phase locked loop frequency synthesizer
MH Perrott, CG Sodini, AP Chandrakasan
US Patent 6,008,703, 1999
A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-TimeADC With VCO-Based Integrator and Quantizer Implemented in 0.13m CMOS
M Park, MH Perrott
IEEE Journal of Solid-State Circuits 44 (12), 3344-3358, 2009
A 1-MHZ bandwidth 3.6-GHz 0.18-/spl mu/m CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise
SE Meninger, MH Perrott
IEEE Journal of Solid-State Circuits 41 (4), 966-980, 2006
Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits
MH Perrott
Proceedings of the 39th annual Design Automation Conference, 498-503, 2002
Photonic subsampling analog-to-digital conversion of microwave signals at 40-GHz with higher than 7-ENOB resolution
J Kim, MJ Park, MH Perrott, FX Kärtner
Optics Express 16 (21), 16509-16515, 2008
A highly digital MDLL-based clock multiplier that leverages a self-scrambling time-to-digital converter to achieve subpicosecond jitter performance
BM Helal, MZ Straayer, GY Wei, MH Perrott
IEEE Journal of Solid-State Circuits 43 (4), 855-863, 2008
A 0.13 µm cmos 78db sndr 87mw 20mhz bw ct δσ adc with vco-based integrator and quantizer
M Park, M Perrott
2009 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2009
A low jitter programmable clock multiplier based on a pulse injection-locked oscillator with a highly-digital tuning loop
BM Helal, CM Hsu, K Johnson, MH Perrott
IEEE Journal of Solid-State Circuits 44 (5), 1391-1400, 2009
An efficient approach to ARMA modeling of biological systems with multiple inputs and delays
MH Perrott, RJ Cohen
IEEE Transactions on Biomedical Engineering 43 (1), 1, 1996
A Temperature-to-Digital Converter for a MEMS-Based Programmable Oscillator With Frequency Stability and Integrated Jitter
MH Perrott, JC Salvia, FS Lee, A Partridge, S Mukherjee, C Arft, J Kim, ...
IEEE Journal of Solid-State Circuits 48 (1), 276-291, 2013
An integrated 2.5 GHz/spl Sigma//spl Delta/frequency synthesizer with 5/spl mu/s settling and 2 Mb/s closed loop modulation
S Wilingham, M Perrott, B Setterberg, A Grzegorek, B McFarland
2000 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2000
Techniques for high data rate modulation and low power operation of fractional-N frequency synthesizers
MH Perrott
Massachusetts Institute of Technology, 1997
An efficient high-resolution 11-bit noise-shaping multipath gated ring oscillator TDC
MZ Straayer, MH Perrott
2008 IEEE Symposium on VLSI Circuits, 82-83, 2008
A low jitter 1.6 GHz multiplying DLL utilizing a scrambling time-to-digital converter and digital correlation
BM Helal, MZ Straayer, GY Wei, MH Perrott
2007 IEEE Symposium on VLSI Circuits, 166-167, 2007
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