| Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI MD Ker IEEE Transactions on Electron Devices 46 (1), 173-183, 1999 | 414 | 1999 |
| A fully integrated 8-channel closed-loop neural-prosthetic CMOS SoC for real-time epileptic seizure control WM Chen, H Chiueh, TJ Chen, CL Ho, C Jeng, MD Ker, CY Lin, ... IEEE journal of solid-state circuits 49 (1), 232-247, 2013 | 326 | 2013 |
| Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes MD Ker, SL Chen, CS Tsai IEEE Journal of solid-state circuits 41 (5), 1100-1107, 2006 | 290 | 2006 |
| Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits MD Ker, KC Hsu IEEE Transactions on device and materials reliability 5 (2), 235-249, 2005 | 281 | 2005 |
| New curvature-compensation technique for CMOS bandgap reference with sub-1-V operation MD Ker, JS Chen IEEE Transactions on circuits and systems II: Express Briefs 53 (8), 667-671, 2006 | 200 | 2006 |
| Fully process-compatible layout design on bond pad to improve wire bond reliability in CMOS Ics MD Ker, JJ Peng IEEE Transactions on components and packaging technologies 25 (2), 309-316, 2002 | 158 | 2002 |
| SCR devices in silicon-on-insulator CMOS process for on-chip ESD protection MD Ker, KK Hung, CY Chang US Patent 6,750,515, 2004 | 144 | 2004 |
| SCR devices with deep-N-well structure for on-chip ESD protection circuits MD Ker, HH Chang, WT Wang US Patent 6,765,771, 2004 | 140 | 2004 |
| Low-voltage-triggered SOI-SCR device and associated ESD protection circuit MD Ker, KK Hung, SC Huang US Patent 6,573,566, 2003 | 136 | 2003 |
| ESD bus lines in CMOS IC's for whole-chip ESD protection MD Ker, HH Chang US Patent 6,144,542, 2000 | 136 | 2000 |
| ESD protection circuit without overstress gate-driven effect MD Ker, HH Chang US Patent 6,249,410, 2001 | 129 | 2001 |
| Complementary LVTSCR ESD protection circuit for sub-micron CMOS integrated circuits MD Ker, CY Wu, HH Chang, CY Lee, J Ko US Patent 5,576,557, 1996 | 119 | 1996 |
| Ultra-high-voltage charge pump circuit in low-voltage bulk CMOS processes with polysilicon diodes MD Ker, SL Chen IEEE Transactions on Circuits and Systems II: Express Briefs 54 (1), 47-51, 2007 | 117 | 2007 |
| CMOS output buffer with CMOS-controlled lateral SCR devices MD Ker, HH Chang US Patent 6,008,684, 1999 | 115 | 1999 |
| A fully integrated 16-channel closed-loop neural-prosthetic CMOS SoC with wireless power and bidirectional data telemetry for real-time efficient human epileptic seizure control CH Cheng, PY Tsai, TY Yang, WH Cheng, TY Yen, Z Luo, XH Qian, ... IEEE Journal of Solid-State Circuits 53 (11), 3314-3326, 2018 | 113 | 2018 |
| On-chip ESD protection circuit with a substrate-triggered SCR device MD Ker, TY Chen, TH Tang US Patent App. 09/682,827, 2003 | 113 | 2003 |
| A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS ICs MD Ker, HH Chang, CY Wu IEEE Journal of Solid-State Circuits 32 (1), 38-51, 1997 | 112 | 1997 |
| Investigation of the gate-driven effect and substrate-triggered effect on ESD robustness of CMOS devices TY Chen, MD Ker IEEE Transactions on Device and Materials Reliability 1 (4), 190-203, 2001 | 109 | 2001 |
| ESD protection circuit with very low input capacitance for high-frequency I/O ports MD Ker, HH Chang, WT Wang US Patent App. 09/944,171, 2002 | 107 | 2002 |
| Latchup-free fully-protected CMOS on-chip ESD protection circuit MD Ker, TS Wu US Patent 5,637,900, 1997 | 107 | 1997 |
