Strain-induced performance improvements in InAs nanowire tunnel FETs F Conzatti, MG Pala, D Esseni, E Bano, L Selmi IEEE transactions on electron devices 59 (8), 2085-2092, 2012 | 117 | 2012 |
Impact of interface traps on the IV curves of InAs tunnel-FETs and MOSFETs: A full quantum study MG Pala, D Esseni, F Conzatti 2012 international Electron devices meeting, 6.6. 1-6.6. 4, 2012 | 87 | 2012 |
Surface-roughness-induced variability in nanowire InAs tunnel FETs F Conzatti, MG Pala, D Esseni IEEE electron device letters 33 (6), 806-808, 2012 | 58 | 2012 |
Investigation of strain engineering in FinFETs comprising experimental analysis and numerical simulations F Conzatti, N Serra, D Esseni, M De Michielis, A Paussa, P Palestri, ... IEEE transactions on electron devices 58 (6), 1583-1593, 2011 | 40 | 2011 |
A simulation study of strain induced performance enhancements in InAs nanowire Tunnel-FETs F Conzatti, MG Pala, D Esseni, E Bano, L Selmi 2011 international electron devices meeting, 5.2. 1-5.2. 4, 2011 | 35 | 2011 |
A 130dB SPL 72dB SNR MEMS microphone using a sealed-dual membrane transducer and a power-scaling read-out ASIC L Sant, M Füldner, E Bach, F Conzatti, A Caspani, R Gaggl, A Baschirotto, ... IEEE Sensors Journal 22 (8), 7825-7833, 2022 | 34 | 2022 |
Experimental and physics-based modeling assessment of strain induced mobility enhancement in FinFETs N Serra, F Conzatti, D Esseni, M De Michielis, P Palestri, L Selmi, ... 2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009 | 33 | 2009 |
Semi-classical transport modelling of CMOS transistors with arbitrary crystal orientations and strain engineering: (Review invited paper) D Esseni, F Conzatti, M De Michielis, N Serra, P Palestri, L Selmi Journal of computational electronics 8, 209-224, 2009 | 17 | 2009 |
Simulation study of the on-current improvements in Ge and sGe versus Si and sSi nano-MOSFETs F Conzatti, P Toniutti, D Esseni, P Palestri, L Selmi 2010 International Electron Devices Meeting, 15.2. 1-15.2. 4, 2010 | 16 | 2010 |
Pseudospectral methods for the efficient simulation of quantization effects in nanoscale MOS transistors A Paussa, F Conzatti, D Breda, R Vermiglio, D Esseni, P Palestri IEEE transactions on electron devices 57 (12), 3239-3249, 2010 | 16 | 2010 |
Investigation of localized versus uniform strain as a performance booster in InAs Tunnel-FETs F Conzatti, MG Pala, D Esseni, E Bano Solid-state electronics 88, 49-53, 2013 | 13 | 2013 |
Drain current improvements in uniaxially strained p-MOSFETs: A multi-subband Monte Carlo study F Conzatti, M De Michielis, D Esseni, P Palestri Solid-state electronics 53 (7), 706-711, 2009 | 13 | 2009 |
Sigma-delta analog-to-digital converter including loop filter having components for feedback digital-to-analog converter correction M Bresciani, JG Kauffman, U Schuetz, P Torta, F Conzatti US Patent 9,866,227, 2018 | 10 | 2018 |
A CT ΔΣ ADC with 9/50MHz BW achieving 73/71dB DR designed for robust blocker tolerance in 14nm FinFET F Conzatti, L Dorrer, P Torta, C Kropf, D Patzold, JSP Garcia, V Rallos, ... ESSCIRC 2017-43rd IEEE European Solid State Circuits Conference, 139-142, 2017 | 9 | 2017 |
System and method for a successive approximation analog-to-digital converter A Paussa, F Conzatti US Patent 10,790,842, 2020 | 6 | 2020 |
On the role of Coulomb scattering in hafnium-silicate gated silicon n and p-channel metal-oxide-semiconductor-field-effect-transistors SM Thomas, MJ Prest, TE Whall, DR Leadley, P Toniutti, F Conzatti, ... Journal of Applied Physics 110 (12), 2011 | 6 | 2011 |
An intrinsically linear 13-level capacitive DAC for delta sigma modulators M Dalla Longa, F Conzatti, T Hofmann, JG Kauffman, M Ortmanns IEEE Transactions on Circuits and Systems II: Express Briefs 70 (4), 1291-1295, 2022 | 5 | 2022 |
On the surface-roughness scattering in biaxially strained n-and p-MOS transistors M De Michielis, F Conzatti, D Esseni, L Selmi IEEE transactions on electron devices 58 (9), 3219-3223, 2011 | 5 | 2011 |
Pseudo-spectral method for the modelling of quantization effects in nanoscale MOS transistors A Paussa, F Conzatti, D Breda, R Vermiglio, D Esseni 2010 International Conference on Simulation of Semiconductor Processes and …, 2010 | 5 | 2010 |
Analog Circuits in 28 nm and 14 nm FinFET L Dörrer, F Kuttner, F Conzatti, P Torta Hybrid ADCs, Smart Sensors for the IoT, and Sub-1V & Advanced Node Analog …, 2018 | 4 | 2018 |